HBM consumes twice the wafers per bit compared to DDR5. This substitution destroys commodity supply while management burns 4 trillion in free cash flow to maintain the HBM lead.
Thesis: The HBM3E ramp and DDR5 mix shift are secondary to the physics of the die-size penalty. Every wafer dedicated to HBM is a wafer removed from the commodity market. This creates a structural supply floor that is being mispriced as a standard cyclical recovery. Effective wafer output is structurally reduced regardless of demand volatility.
Verdict: LONG — Conviction: MEDIUM
Catalyst: HBM3E mass production ramp in H1 2024 and inventory normalization in DRAM by the end of H1.
Key Risk: Downstream capacity constraints in TSMC CoWoS packaging preventing die-stack shipments from converting to revenue.
The Tell: Management admitted the HBM price premium might be less this year than last due to general DRAM price increases. They are losing the exclusive premium narrative as the broader market recovers and are using HBM3E complexity as a new justification for future premiums.
Friction Level: MODERATE_FRICTION — The friction lies in whether HBM demand is a structural shift or a lumpy training cycle. The bull case relies on a permanent wafer penalty floor while the bear case identifies a TSMC CoWoS packaging bottleneck and lumpy hyperscaler CapEx as the true constraints.
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