They raised full-year guidance by ¥10 billion, but every yen came from a product segment they explicitly cannot manufacture fast enough.
Thesis: This is no longer a broad semiconductor play; it is a leveraged bet on HBM complexity. The street is obsessing over the cyclical delay in smartphone/PC SoC testers, missing the structural explosion in memory test intensity. Advantest is the bottleneck for HBM yield. When NVDA needs HBM3E, they need Advantest. The 'delayed' SoC recovery is just operating leverage coiled for 2H 2024.
Verdict: LONG — Conviction: HIGH
Catalyst: TSMC's CoWoS capacity ramp hitting full stride in June/July 2024, forcing a tester order inflection for the SoC segment to match the HBM ramp.
Key Risk: Manufacturing execution on memory testers. Management admitted they are the bottleneck. If they can't ship, they cap their own upside while legacy segments drag.
The Tell: The admission of internal incompetence on HBM supply: 'We are not at the stage that we are able to provide sufficient supply.' Usually, a CEO blames the supply chain. Here, they admitted the constraint is their own manufacturing floor in Japan.
Friction Level: MODERATE_FRICTION — Bulls see an HBM monopoly with pricing power; Bears see a one-trick pony waiting for a cyclical SoC recovery that keeps getting pushed out.
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