They just proved they own the thermal bottleneck at 2nm, and the street is still obsessing over quarterly fluctuations in China.
Thesis: Physics is the moat. As nodes shrink to 2nm, thermal budgets collapse. Veeco's LSA/NSA is not optional; it's the only way to anneal without frying the wafer. They are using 37% trailing-edge China revenue to subsidize their lock-in at the 2nm gate-all-around node. The 'flat' 2024 guidance masks a mix shift from commodity capacity to high-margin monopoly pricing. You buy the bottleneck before the volume ramp.
Verdict: LONG — Conviction: HIGH
Catalyst: Confirmation of the second memory customer evaluation turning into a High Volume Manufacturing (HVM) order in late 2024/early 2025.
Key Risk: China revenue (37%) falls off a cliff due to export controls before the GAA/HBM ramp fully offsets it, creating a revenue air pocket.
The Tell: When asked about HBM logic steps applying to standard DDR5, CEO Miller admitted, 'That's the area I don't have crystal clear understanding.' He's not selling a dream he doesn't have yet; he's selling the specific HBM bottleneck he owns.
Friction Level: MODERATE_FRICTION — Street models 2024 as 'flat transition'; I see a structural lock-in of the thermal budget at 2nm that guarantees 2025 margin expansion.
Report not found
The report data is no longer available. Please return to the archive.